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Features
* High Performance, Low Power AVR(R) 8-Bit Microcontroller * Advanced RISC Architecture
- 120 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation Non-Volatile Program and Data Memories - 4K Bytes of In-System Programmable Program Memory Flash - 64 Bytes of In-System Programmable EEPROM - 256 Bytes of Internal SRAM - Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM - Data retention: 20 years at 85C/ 100 years at 85C(1) - Programming Lock for Software Security Peripheral Features - Two 8-Bit Timer/Counters with two PWM Channels, Each - Programmable Watchdog Timer with Separate On-chip Oscillator - On-Chip Analog Comparator - 10-bit ADC 4 Single-Ended Channels - Universal Serial Interface - Boost Converter Special Microcontroller Features - debugWIRE On-chip Debug System - In-System Programmable via SPI Port - External and Internal Interrupt Sources - Pin Change Interrupt on 16 Pins - Low Power Idle, ADC Noise Reduction and Power-Down Modes - Enhanced Power-On Reset Circuit - Programmable Brown-Out Detection Circuit - Internal Calibrated Oscillator - Temperature Sensor On Chip I/O and Packages - Available in 20-Pin SOIC and 20-Pin QFN/MLF - 16 Programmable I/O Lines Operating Voltage: - 0.7 - 1.8V (via On-Chip Boost Converter) - 1.8 - 5.5V (Boost Converter Bypassed) Speed Grade - Using On-Chip Boost Converter 0 - 4 MHz - External Power Supply 0 - 4 MHz @ 1.8 - 5.5V 0 - 8 MHz @ 2.7 - 5.5V Low Power Consumption - Active Mode, 1 MHz System Clock (Without Boost Converter) 400 A @ 3V - Power-Down Mode (Without Boost Converter) 150 nA @ 3V 1. See "Data Retention" on page 6 for details.
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8-bit Microcontroller with 4K Bytes In-System Programmable Flash and Boost Converter ATtiny43U Preliminary Summary
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Note:
Rev. 8048BS-AVR-03/09
1. Pin Configurations
Figure 1-1. Pinout of ATtiny43U
SOIC
(T0/PCINT8) PB0 (OC0A/PCINT9) PB1 (OC0B/PCINT10) PB2 (T1/CLKO/PCINT11) PB3 (DI/OC1A/PCINT12) PB4 (DO/OC1B/PCINT13) PB5 (USCK/SCL/PCINT14) PB6 (INT0/PCINT15) PB7 VCC GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA7 (RESET/dW/PCINT7) PA6 (CLKI/PCINT6) PA5 (AIN1/PCINT5) PA4 (AIN0/PCINT4) PA3 (ADC3/PCINT3) PA2 (ADC2/PCINT2) PA1 (ADC1/PCINT1) PA0 (ADC0/PCINT0) VBAT LSW
QFN/MLF Top View
PB0 (T0/PCINT8) PA7 (RESET/dW/PCINT7) PA6 (CLKI) PA5 (AIN1/PCINT5) 15 14 13 12 11 6 7 8 9 10
PB1 (OC0A/PCINT9)
(OC0B/PCINT9) PB2
(T1/CLKO/PCINT11) PB3 (DI/OC1A/PCINT12) PB4 (DO/OC1B/PCINT13) PB5 (USCK/SCL/PCINT14) PB6
1 2 3 4 5
20 19 18 17 16
PA4 (AIN0/PCINT4) PA3 (ADC3/PCINT3) PA2 (ADC2/PCINT2) PA1 (ADC1/PCINT1) PA0 (ADC0/PCINT0)
NOTE: Bottom pad should be Soldered to ground.
1.1
1.1.1
Pin Descriptions
VCC Supply voltage.
1.1.2
GND Ground.
1.1.3
Port A (PA7:PA0) Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source
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(INT0/PCINT15) PB7
VCC GND LSW VBAT
capability except PA7 which has the RESET capability. To use pin PA7 as an I/O pin, instead of RESET pin, program (`0') RSTDISBL fuse. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has an alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in "Alternate Port Functions" on page 67. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 20-4 on page 158. Shorter pulses are not guaranteed to generate a reset. 1.1.5 Port B (PB7:PB0) Port B is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features as listed in Section 11.3 "Alternate Port Functions" on page 67. 1.1.6 LSW Boost converter external inductor connection. Connect to ground when boost converter is disabled permanently. 1.1.7 VBAT Battery supply voltage. Connect to ground when boost converter is disabled permanently.
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2. Overview
The ATtiny43U is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny43U achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. Block Diagram
VCC RESET
VBAT LSW GND
BOOST CONVERTER
POWER SUPERVISION
POR BOD RESET
INTERNAL OSCILLATOR
CALIBRATED OSCILLATOR
WATCHDOG TIMER
TIMING AND CONTROL
PROGRAMMING LOGIC
PROGRAM COUNTER
MCU CONTROL REGISTER
PROGRAM FLASH
STACK POINTER
MCU STATUS REGISTER
INSTRUCTION REGISTER
SRAM
TIMER/ COUNTER0
INSTRUCTION DECODER
GENERAL PURPOSE REGISTERS
X Y Z
TIMER/ COUNTER1
CONTROL LINES
INTERRUPT UNIT
ANALOG COMPARATOR
ON-CHIP DEBUG
ALU
EEPROM
VOLTAGE REFERENCE
ISP INTERFACE
STATUS REGISTER
USI
ADC
DATA REGISTER PORT A
DIRECTION REG. PORT A
DATA REGISTER PORT B
DIRECTION REG. PORT B
DRIVERS PORT A
DRIVERS PORT B
PA7:0
PB7:0
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting
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architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny43U provides the following features: 4K byte of In-System Programmable Flash, 64 bytes EEPROM, 256 bytes SRAM, 16 general purpose I/O lines, 32 general purpose working registers, two 8-bit Timer/Counters with two PWM channels, Internal and External Interrupts, a 4-channel 10-bit ADC, Universal Serial Interface, a programmable Watchdog Timer with internal Oscillator, internal calibrated oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. A special feature of ATtiny43U is the built-in boost voltage converter, which provides 3V supply voltage from an external, low voltage. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny43U AVR is supported by a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
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3. About
3.1 Resources
A comprehensive set of development tools, drivers and application notes, and datasheets are available for download on http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
3.3
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C.
3.4
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
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4. Register Summary
Address
0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20)
Name
SREG SPH SPL OCR0B GIMSK GIFR TIMSK0 TIFR0 SPMCSR OCR0A MCUCR MCUSR TCCR0B TCNT0 OSCCAL TCCR0A TCCR1A TCCR1B TCNT1 OCR1A OCR1B Reserved Reserved Reserved DWDR CLKPR Reserved Reserved GTCCR Reserved WDTCSR PCMSK1 Reserved EEAR EEDR EECR PORTA DDRA PINA PORTB DDRB PINB GPIOR2 GPIOR1 GPIOR0 PCMSK0 Reserved USIBR USIDR USISR USICR TIMSK1 TIFR1 Reserved Reserved ACSR ADMUX ADCSRA ADCH ADCL ADCSRB Reserved DIDR0 PRR
Bit 7
I - SP7 - - - - - BODS - FOC0A CAL7 COM0A1 COM1A1 FOC1A
Bit 6
T - SP6 INT0 INTF0 - - - PUD - FOC0B CAL6 COM0A0 COM1A0 FOC1B
Bit 5
H -
Bit 4
S -
Bit 3
V -
Bit 2
N -
Bit 1
Z - SP1 - - OCIE0A OCF0A PGERS ISC01 EXTRF CS01 CAL1 WGM01 WGM11
Bit 0
C SP8 SP0 - - TOIE0 TOV0 SPMEN ISC00 PORF CS00 CAL0 WGM00 WGM10 CS10
Page
Page 8 Page 12 Page 12 Page 95 Page 60 Page 60 Page 95 Page 96 Page 137 Page 95
Page 34, Page 59, Page 78
SP5 SP4 SP3 SP2 Timer/Counter0 - Output Compare Register B PCIE1 PCIF1 - - - PCIE0 PCIF0 - - - - - - - - OCIE0B OCF0B
CTPB RFLB PGWRT Timer/Counter0 - Output Compare Register A SM1 - - CAL4 COM0B0 COM1B0 - SM0 WDRF WGM02 CAL3 - - WGM12 CS12 BODSE BORF CS02 CAL2
SE - - CAL5 COM0B1 COM1B1 -
Page 54 Page 93 Page 94 Page 28 Page 90 Page 90 Page 93 Page 95 Page 95 Page 95
Timer/Counter0
CS11
Timer/Counter1 Timer/Counter1 - Output Compare Register A Timer/Counter1 - Output Compare Register B - - - DWDR[7:0] CLKPCE - - - - - TSM WDIF PCINT15 - - PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 - WDIE PCINT14 - - PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 - WDP3 PCINT13 EEAR5 EEPM1 PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 - - WDCE PCINT12 - EEAR4 EEPM0 PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 EEAR3 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 EEAR2 EEMPE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 EEAR1 EEPE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 EEAR0 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 WDE PCINT11 WDP2 PCINT10 WDP1 PCINT9 WDP0 PCINT8 - - - PSR10 CLKPS3 CLKPS2 CLKPS1 CLKPS0
Page 132 Page 28
Page 99 Page 54 Page 61 Page 20 Page 21 Page 21 Page 78 Page 78 Page 78 Page 78 Page 78 Page 78 Page 22 Page 22 Page 22
EEPROM Data Register
General Purpose I/O Register 2 General Purpose I/O Register 1 General Purpose I/O Register 0 PCINT7 PCINT6 PCINT5 PCINT4 - USI Buffer Register USI Data Register USISIF USISIE - - USIOIF USIOIE - - USIPF USIWM1 - - USIDC USIWM0 - - - - ACD - ADEN ACBG REFS ADSC ACO - ADATE ACI - ADIF ACIE - ADIE - MUX2 ADPS2 ACIS1 MUX1 ADPS1 ACIS0 MUX0 ADPS0 USICNT3 USICS1 - - USICNT2 USICS0 OCIE1B OCF1B USICNT1 USICLK OCIE1A OCF1A USICNT0 USITC TOIE1 TOV1 PCINT3 PCINT2 PCINT1 PCINT0
Page 61 Page 111 Page 112 Page 112 Page 112 Page 96 Page 96
Page 113 Page 126 Page 127 Page 128 Page 128
ADC Data Register High Byte ADC Data Register Low Byte BS ACME - AIN1D PRE2 PRE1 PRE0 ADLAR - AIN0D - ADC3D PRTIM1 ADC2D PRTIM0 ADC1D PRUSI ADC0D PRADC - ADTS2 ADTS1 ADTS0
Pages 47, 113, 129 Page 114, Page 130 Page 35
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Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
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5. Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID SBI CBI LSL LSR ROL Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k P,b P,b Rd Rd Rd k
Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k Add two Registers
Description
Rd Rd + Rr
Operation
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 1
ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7)
BRANCH INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
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Mnemonics
ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH
Operands
Rd Rd Rd s s Rr, b Rd, b Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear
Description
Rotate Right Through Carry
Operation
Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (z) R1:R0 Rd P P Rr STACK Rr Rd STACK
Flags
Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 1 1 1 N/A
Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP NOP SLEEP WDR BREAK Rd, P P, Rr Rr Rd Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/Timer) For On-chip Debug Only
MCU CONTROL INSTRUCTIONS None None None
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6. Ordering Information
6.1 ATtiny43U
Speed (MHz) 8 Notes: Power Supply 1.8 - 5.5V (3) Ordering Code (1) ATTINY43U-MU ATtiny43U-SU Package (2) 20M1 20S2 Operational Range Industrial (-40C to 85C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Supply voltage on VCC pin, boost converter disregarded. When boost converter is active the device can be operated from voltages sources lower than indicated here. See table "Characteristics of Boost Converter. T = -20C ... +85C, unless otherwise noted" on page 159 for more information.
Package Type 20M1 20S2 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 20-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
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7. Packaging Information
7.1 20M1
D
1 Pin 1 ID 2 3
E
SIDE VIEW
TOP VIEW A2 D2 A1 A
1 Pin #1 Notch (0.20 R) 2 3
0.08
C
E2
SYMBOL A A1
COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.70 - NOM 0.75 0.01 0.20 REF 0.18 0.23 4.00 BSC 2.45 2.60 4.00 BSC 2.45 2.60 0.50 BSC 0.35 0.40 0.55 2.75 2.75 0.30 MAX 0.80 0.05 NOTE
b
L e BOTTOM VIEW
A2 b D D2 E E2 e
Note:
Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
L
10/27/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 20M1 REV. A
R
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7.2
20S2
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8. Errata
The revision letter in this section refers to the revision of the ATtiny43U device.
8.1
8.1.1
ATtiny43U
Rev. C * Increased Probability of Boost Converter Entering Active Low Current Mode 1. Increased Probability of Boost Converter Entering Active Low Current Mode The boost converter may enter and stay in Active Low Current Mode at supply voltages and load currents higher than those specified. This is due to high switching currents in bonding wires of the SOIC package. Devices packaged in MLF are not affected. Problem Fix / Workaround Add a 1.5nF capacitor between pins LSW and GND of the SOIC package. Also, increase the value of the by-pass capacitor between pins VCC and GND to at least 30F. Alternatively, use the device in MLF, without modifications.
8.1.2
Rev. B Not sampled.
8.1.3
Rev. A Not sampled.
14
ATtiny43U
8048BS-AVR-03/09
9. Datasheet Revision History
9.1 Rev. 8048B-03/09
1.
Updated Data retention bullet in "Features" on page 1.
9.2
Rev. 8048A-02/09
1.
Initial revision.
15
8048BS-AVR-03/09
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8048BS-AVR-03/09

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